Output buffer circuit and control method therefor

Details Output buffer circuit and control method therefor Output buffer circuit and control method therefor

2005-08-02

2005-08-02

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S083000, C326S027000

Reexamination Certificate

active

06924669

ABSTRACT:
An output buffer includes a first drive circuit that receives an input signal having a sharp waveform and generates an output signal that has a gentle waveform. A second drive circuit is connected to the first drive circuit at an output terminal and has a lower impedance than the first drive circuit. A delay circuit is also connected to the output terminal and generates a delayed output signal. A first control circuit is connected between the delay circuit and the second drive circuit and receives the input signal and the delayed output signal and generates a first control signal used to drive the second drive circuit.

REFERENCES:
patent: 4779013 (1988-10-01), Tanaka
patent: 5166555 (1992-11-01), Kano
patent: 5319260 (1994-06-01), Wanlass
patent: 5877638 (1999-03-01), Lin
patent: 6281706 (2001-08-01), Wert et al.
patent: A-2-241114 (1990-09-01), None
patent: 11-250244 (1995-06-01), None

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