Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-02-22
2005-02-22
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S321000, C257S410000
Reexamination Certificate
active
06858899
ABSTRACT:
A thin film transistor includes an insulating substrate, an active layer located over the substrate, a gate electrode located over the substrate; and a charge storage region located between the active layer and the gate electrode. The charge storage region includes a tunneling dielectric located adjacent to the active layer, a blocking dielectric located adjacent to the gate electrode and a charge storage dielectric located between the tunneling dielectric and the blocking dielectric. At least one of the tunneling dielectric, the charge storage dielectric and the blocking dielectric comprises a layer having a dielectric constant greater than 3.9, such as a metal oxide layer.
REFERENCES:
patent: 5306935 (1994-04-01), Esquivel et al.
patent: 5691552 (1997-11-01), Oyama
patent: 5889302 (1999-03-01), Liu
patent: 6185122 (2001-02-01), Johnson et al.
patent: 6191459 (2001-02-01), Hoffmann et al.
patent: 6248635 (2001-06-01), Foote et al.
patent: 6285586 (2001-09-01), Lung et al.
patent: 6285596 (2001-09-01), Miura et al.
patent: 6288419 (2001-09-01), Prall et al.
patent: 6297143 (2001-10-01), Foote et al.
patent: 6301155 (2001-10-01), Fujiwara
patent: 6313503 (2001-11-01), Lee et al.
patent: 6319775 (2001-11-01), Halliyal et al.
patent: 6326268 (2001-12-01), Park et al.
patent: 6348380 (2002-02-01), Weimer et al.
patent: 6593624 (2003-07-01), Walker
patent: 6617639 (2003-09-01), Wang et al.
patent: 6630383 (2003-10-01), Ibok et al.
patent: 6660588 (2003-12-01), Yang et al.
patent: 20010030340 (2001-10-01), Fujiwara
patent: 20010041250 (2001-11-01), Werkhoven et al.
patent: 20010041434 (2001-11-01), Nakamura
patent: 20010046738 (2001-11-01), Au et al.
patent: 20010052615 (2001-12-01), Fujiwara
patent: 20010055838 (2001-12-01), Walker et al.
patent: 20020000592 (2002-01-01), Fujiwara
patent: 20020020890 (2002-02-01), Willer
patent: 20020024092 (2002-02-01), Palm et al.
patent: 20020028541 (2002-03-01), Lee et al.
patent: 20020033501 (2002-03-01), Sakagami
U.S. Provisional application No. 60/412,739.*
Non-Volatile Semiconductor Workshop, Feb. 16-20, 2003, Monterey, California, NVSMW Conference Schedule/Program.
Improved SONOS-type Flash Memory using HfO2as Trapping Layer, Min She, et al, Non-Volatile Semiconductor Workshop, Feb. 16-20, 2003, Monterey, California, p. 53.
High Reliable SONOS-type NAND Flash Memory Cell with Al2O3for Top Oxide, Yoocheol Shin, et al, Non-Volatile Semiconductor Workshop, Feb. 16-20, 2003, Monterey, California, p. 58.
New 2-bit/Tr MONOS Type Flash Memory using Al2O3as Charge Trapping Layer, Taro Sugizaki, et al, Non-Volatile Semiconductor Workshop, Feb. 16-20, 2003, Monterey, California, p. 60.
Flash Memory Cell with LaA103(k=27.5) as Tunneling Dielectrics for beyond Sub-50 nm Technology, Yaohui Zhang, et al., Non-Volatile Semiconductor Workshop, Feb. 16-20, 2003, Monterey, California, p. 75.
A novel low voltage memory device with an engineered SiO2/high-k tunneling barrier, P. Bloome et al., Non-Volatile Semiconductor Workshop, Feb. 16-20, 2003, Monterey, California, p. 94.
Characterization of the Aluminum-Tantalum Oxide-Silicon Dioxide-Silicon Charge Storage (MTOS) Device, R.L. Angle, G.E. Talley, IEDM 1988 Proc. p. 466-468.
CMOS Metal Replacement Gate Transistors Using Tantalum Pentoxide Gate Insulator, A. Chatterjee, et al, IEDM 1998 Proc. p. 29.1.1-29.1.4.
Deposited Inter-Polysilicon Dielectrics for Nonvolatile Memories, Johan H. Klootwijk, Member, IEEE, et al., IEEE Transactions on Electron Devices, vol. 46, No. 7, Jul. 1999, p. 1435-1445.
Mahajani Maitreyee
Walker Andrew J.
Foley & Lardner LLP
Matrix Semiconductor Inc.
Prenty Mark V.
LandOfFree
Thin film transistor with metal oxide layer and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Thin film transistor with metal oxide layer and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Thin film transistor with metal oxide layer and method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3446984