Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-05-17
2005-05-17
Nguyen, Thanh (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000, C438S638000, C438S641000, C438S685000, C438S688000
Reexamination Certificate
active
06893957
ABSTRACT:
A dual damascene process is disclosed, in which a contact via and trench pattern is etched into insulating layer(s). The via is first partially filled by selective metal (e.g., tungsten) deposition, thereby forming a partial plug that raises the floor and reduces the effective aspect ratio of the trench and via structure. The remaining portion of the contact via is then filled with a more conductive material (e.g., aluminum). This deposition also at least partially fills the overlying trench to form metal runners. In the illustrated embodiment, hot aluminum deposition fills the portion of the contact via left unoccupied by the selective deposition and overfills into the trench. A further, cold aluminum deposition then follows, topping off the trench prior to planarization. The dual damascene structure thus exhibits a raised floor relative to conventional dual damascene metallization, while still retaining the conduction benefits of aluminum through a significant portion of the contact and the metal runner formed in the trench.
REFERENCES:
patent: 4804560 (1989-02-01), Shioya et al.
patent: 5677237 (1997-10-01), Tsai et al.
patent: 5714804 (1998-02-01), Miller et al.
patent: 5739579 (1998-04-01), Chiang et al.
patent: 5840625 (1998-11-01), Feldner
patent: 5990011 (1999-11-01), McTeer
patent: 6028362 (2000-02-01), Omura
patent: 6156651 (2000-12-01), Havemann
patent: 6211085 (2001-04-01), Liu
patent: 6235603 (2001-05-01), Melnick et al.
patent: 6239021 (2001-05-01), Pramanick et al.
patent: 6258707 (2001-07-01), Uzoh
patent: 6271596 (2001-08-01), Alers
patent: 6365514 (2002-04-01), Yu et al.
patent: 6380073 (2002-04-01), Hwang et al.
patent: 20020195715 (2002-12-01), Cho
patent: 9532478 (1995-02-01), None
patent: 8227939 (1996-09-01), None
Miller et al., “CVD Tungsten Interconnect and Contact Barrier Technology for VLSI,” Solid State Technology, Dec. 1982, pp. 85-90.
Saraswat, et al. “Selective CVD of Tungsten for VLSI Technology,” Journal of the Electrochemical Society, vol. 131, No. 3, 1984, pp. 409-419.
Stacy et al.“Interfacial Structure of Tungsten Layers Formed by Selective Low Pressure Chemical Vapor Deposition,” J. Electrochem. Soc.: Solid State Science and Technology, vol. 132, No. 2, Feb. 1985, pp. 444-448.
Trivedi Jigish D.
Violette Mike P.
Knobbe Martens Olson & Bear LLP
Nguyen Thanh
LandOfFree
Method of forming a dual damascene interconnect by selective... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming a dual damascene interconnect by selective..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming a dual damascene interconnect by selective... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3446916