Semiconductor device verification system and method

Details Semiconductor device verification system and method Semiconductor device verification system and method

2005-03-22

2005-03-22

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C716S030000

Reexamination Certificate

active

06870781

ABSTRACT:
A semiconductor device verification system and method isolates errors detected during verification by comparing a predetermined stimulus applied to the semiconductor device with an observed stimulus measured within the semiconductor device. If the predetermined stimulus differs from the observed stimulus, the error likely results from an inaccuracy in the verification process rather than a flaw of the semiconductor device. The observed stimulus is measured between the input circuit and the core of the semiconductor device, such as between the flip flop associated with an input pin and the logic core of a processor. An observed stimulus circuit integrated within the semiconductor device outputs the observed stimulus to an output pin for use by an error isolation engine associated with verification testing equipment.

REFERENCES:
patent: 5668745 (1997-09-01), Day
patent: 6775810 (2004-08-01), Chang et al.
patent: 20040163059 (2004-08-01), Subbarayan
Josephson, Don Douglas; Poehlman, Steve; Govan, Vincent “Debug Methodology for the McKinley Processor” Paper 16.2, ITC International Test Conference 0-7803-7169-0/01 2001.

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