Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-05-10
2005-05-10
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06892374
ABSTRACT:
In one embodiment, the present invention relates to a system for generating an artwork representation according to a circuit fabrication process. The system comprises a cell library that stores at least dimensional information associated with a plurality of circuit cells, wherein each of the plurality of circuit cells is defined by a sub-mask for a respective logical device according to the circuit fabrication process; an instance placement engine that generates a circuit layout that is defined by at least a specification file specifying an arrangement of logical devices and the cell library; and an artwork generator that generates an artwork representation that defines a mask for etching of the generated circuit layout according to the circuit fabrication process.
REFERENCES:
patent: 5197016 (1993-03-01), Sugimoto et al.
patent: 5303161 (1994-04-01), Burns et al.
patent: 5461576 (1995-10-01), Tsay et al.
patent: 5533179 (1996-07-01), Kucukcakar et al.
patent: 5551014 (1996-08-01), Yoshida et al.
patent: 5666288 (1997-09-01), Jones et al.
patent: 5726902 (1998-03-01), Mahmood et al.
patent: 5764530 (1998-06-01), Yokomaku
patent: 6470482 (2002-10-01), Rostoker et al.
patent: 20020060296 (2002-05-01), Van Der Veen
patent: 20020108097 (2002-08-01), Harris et al.
NN70101084, “Producing integrated circuits from a circuit logic input”, Octiber 1970, IBM Technical Disclosure Bulletin, vol. No.: 13, Issue No.: 5, pp.: 1084-1089.*
Hernifer et al., “PC board design anf fabrication using schematics, PADS-preform, and a laser printer”, Nov. 2-6, 1994, Frontiers in Education Conference, 25-th Annual Conference, pp.: 111-115.*
Cook et al., “Automatic artwork generation for large scale integration”, 4, Dec. 1967 Solid-State Circuits, IEEE Journal of , vol.: 2, Issue: 4, pp.:190-196.*
United Kingdom Search Report for Application No. GB 0313221.4 dated Oct. 28, 2003.
Biggio Matthew L.
Burden David C.
Melli Bruno P.
Rossoshek Helen
Thompson A. M.
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