Semiconductor memory circuitry

Details Semiconductor memory circuitry Semiconductor memory circuitry

2005-05-31

2005-05-31

Wille, Douglas (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000

Reexamination Certificate

active

06900493

ABSTRACT:
Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. Considerably greater numbers of die sites per wafer are achieved for 6-inch, 8-inch and 12-inch wafers for 4M, 16M, 64M, and 256M integration levels. Further, an integrated circuit includes a semiconductor die, a plurality of functional and operably addressable memory cells arranged in at least one array formed on the semiconductor die, and circuitry formed on the semiconductor die and coupled to the memory cells for permitting data to be written to and read from the memory cells, wherein at least one area of 100 square microns of continuous surface area of the die has at least 170 of the memory cells.

REFERENCES:
patent: 3725842 (1973-04-01), Feldberg
patent: 4956307 (1990-09-01), Pollack et al.
patent: 5006909 (1991-04-01), Kosa
patent: 5013680 (1991-05-01), Lowrey et al.
patent: 5055898 (1991-10-01), Beilstein, Jr. et al.
patent: 5107459 (1992-04-01), Chu et al.
patent: 5128737 (1992-07-01), van der Have
patent: 5287000 (1994-02-01), Takahashi et al.
patent: 5326715 (1994-07-01), Jang et al.
patent: 5338897 (1994-08-01), Tsay et al.
patent: 5360753 (1994-11-01), Park et al.
patent: 5396450 (1995-03-01), Takashima et al.
patent: 5407534 (1995-04-01), Thakur
patent: 5519238 (1996-05-01), Lu
patent: 5555212 (1996-09-01), Toshiaki et al.
patent: 5555519 (1996-09-01), Takashima et al.
patent: 5610418 (1997-03-01), Eimori
patent: 5629230 (1997-05-01), Fazan et al.
patent: 5654577 (1997-08-01), Nakamura et al.
patent: 5767521 (1998-06-01), Takeno et al.
patent: 5770500 (1998-06-01), Batra et al.
patent: 5838038 (1998-11-01), Takashima et al.
patent: 5864181 (1999-01-01), Keeth
patent: 5866453 (1999-02-01), Prall et al.
patent: 6043562 (2000-03-01), Keeth
patent: 6084307 (2000-07-01), Keeth
patent: 6222275 (2001-04-01), Keeth
patent: 6243311 (2001-06-01), Keeth
patent: 6288421 (2001-09-01), Keeth et al.
patent: 6392303 (2002-05-01), Keeth
patent: 6429529 (2002-08-01), Keeth
patent: 2058377 (1990-02-01), None
patent: 3116865 (1991-05-01), None
patent: 6216343 (1994-08-01), None
patent: 7093990 (1995-04-01), None
Eimori et al. “A Newly Designed Planar Stacked Capacitor Cell with High Dielectric Constant Film for 256 Mbit DRAM” IEDM 1993, pp 26.3.1-.4.*
Eimori et al., “A Newly Designed Planar Stacked Capacitor Cell with High Dielectric Constant Film for 256MBit DRAM,” IEDM 1993, pp. 26.3.1-.4.
Kitsukawa et al., “256-Mb DRAM Circuit Technologies For File Applications”, IEEE Journal of Solid-State Circuits, vol. 28, No. 11, Nov. 1993, pp. 1105-1113.
Sugibayashi et al., “A 30-ns 256-Mb DRAM With A Multidivided Array Structure”, IEEE Journal of Solid-State Circuits, vol. 28, No. 11, Nov. 1993, pp. 1092-1098.
Anthony Denboer, “Inside Today's Leading Edge Microprocessors,” Semiconductor International, Feb. 1994.
European Search Report completed Feb. 26, 2003 for European Application No. EP 03,001,319.
Watanabe, S., et al., “A Novel Circuit Technology with Surrounding Gate Transistors (SGTs) For Ultra High Density DRAM'S,” IEEE Journal of Solid-State Circuits, vol. 30, No. 9, Sep. 1, 1995, IEEE Inc., New York, NY, pp. 960-970.
Sunouchi, K., et al., “A Surrounding Gate Transistor (SGT) cell for 64/256 Mbit DRAMs,” EEDM 89-23, 1989, IEEE Inc., New York, NY, pp. 2.1.1-2.1.4.
Hamamoto, T., et al., “NAND-Structured Trench Capacitor Cell Technologies for 256MB DRAM and Beyond,” IEICE Transactions on Electronics, Institute of Electronics Information and Comm. Eng. Tokyo, JP, vol. E78-C, NR. 7 Jul. 1995, pp. 789-796.
Asakura, M., “An Experimental 256-Mb DRAM with Boosted Sense-Ground Scheme,” IEEE Journal of Solid-State Circuits, vol. 29, No. 11, Nov. 1994, IEEE Inc., New York, NY, pp. 1303-1309.
JPO Notice of Reasons for Rejection, dated Jul. 6, 2004.

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