Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-08-09
2005-08-09
Ellis, Kevin L. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
06928519
ABSTRACT:
A mechanism and method for maintaining cache consistency in computer systems. When a request transfers exclusive access to a cache block from an active device D1to a second active device D2,the sending of the data from D1terminates D1's access rights to the block and the reception of the data at D2initiates its access rights. When a request changes exclusive access to a cache block at an active device D1to a shared state with an active device D2,the sending of the data from D1terminates D1's exclusive access right and the arrival of the data at D2initiates its access rights. When a request transfers a cache block from a shared state to exclusive access at an active device D2,the access rights at all active devices other than D2and the active device which owns the cache block are terminated upon reception of the request, the access right of the active device that owns the cache block is terminated when it sends the data, and the exclusive access right at D2is initiated when D2has received the data from the previous owner.
REFERENCES:
patent: 5761721 (1998-06-01), Baldus et al.
patent: 5802582 (1998-09-01), Ekanadham et al.
patent: 5978874 (1999-11-01), Singhal et al.
patent: 6088768 (2000-07-01), Baldus et al.
patent: 6209064 (2001-03-01), Weber
patent: 6484240 (2002-11-01), Cypher et al.
patent: 2004/0003180 (2004-01-01), Cypher
patent: 2004/0003181 (2004-01-01), Cypher
patent: 2004/0003183 (2004-01-01), Cypher et al.
U.S. Appl. No. 10/821,564, filed Apr. 9, 2004.
“Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol”, Sorin, et al,IEEE Transactions on Parallel and Distributed Systems, vol. 13, No. 6, Jun. 2002, http://www.cs.wisc.edu/multifacet/papers/tpds02_lamport.pdf.
“Multicast Snooping: A New Coherence Method Using a Multicast Address Network”, Bilir, et al,The 26thInternational Symposium on Computer Architecture, IEEE, Atlanta, GA, May 2-4, 1999, http://csdl.computer.org/comp/proceedings/isca/1999/0170/00/01700294abs.htm.
“Architecture and Design of AlphaServer GS320”, Gharachorloo, et al,ACM Sigplan Notices, vol. 35, Issue 11, Nov. 2000, http://portal.acm.org/citation.cfm?id=356991&dl=ACM&coll=portal.
“View Caching: Efficient Software Shared Memory for Dynamic Computations”, Karamcheti, et al,11thInternational Parallel Processing Symposium, Geneva, Switzerland, Apr. 1-5, 1997, http://ipdps.eece.unm.edu/1997/s13/318.pdf.
“Cache-Coherent Distributed Shared Memory: Perspectives on Its Development and Future Challenges”, Hennessy, et al,Proceedings of the IEEE, vol. 87, Issue 3, Mar. 1999, ISSN 0018-9219, http://cva.stanford.edu/cs99s/papers/hennessy-cc.pdf.
“Survey on Cache Coherence in Shared & Distributed Memory Multiprocessors”, Garg, et al, Online, http://www.cse.psu.edu/˜cg530/proj03/cache_coherence.pdf.
“A Survey of Cache Coherence Mechanisms in Shared Memory Multiprocessors”, Lawrence, Department of Computer Science, University of Manitoba, Manitoba, Canada, May 14, 1998, http://www.cs.uiowa.edu/˜rlawrenc/research/Papers/cc.pdf.
“Bandwidth Adaptive Snooping”, Martin, et al.8thAnnual International Symposium on High-Performance Computer Architecture(HPCA-8), Cambridge, MA, Feb. 2-6, 2002.
“Timestamp Snooping: An Approach for Extending SMPs”, Martin, et al.,9thInternational Conference on Architectural Support for Programming Languages and Operating Systems(ASPLOS-IX), Cambridge, MA, Nov. 13-15, 2000.
“Isotach Networks”, Reynolds, et al., IEEE Transactions on Parallel and Distributed Systems, vol. 8, No. 4, Apr. 1997.
Ellis Kevin L.
Kivlin B. Noäl
Meyertons Hood Kivlin Kowert & Goetzel P.C.
LandOfFree
Mechanism for maintaining cache consistency in computer systems does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Mechanism for maintaining cache consistency in computer systems, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mechanism for maintaining cache consistency in computer systems will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3441100