Single event hardening of null convention logic circuits

Details Single event hardening of null convention logic circuits Single event hardening of null convention logic circuits

2005-08-30

2005-08-30

Mai, Lam T. (Department: 2819)

Electronic digital logic circuitry

Reliability

Fail-safe

C326S121000, C326S093000

Reexamination Certificate

active

06937053

ABSTRACT:
A system and method for hardening a Null Convention Logic (NCL) circuit against Single Event Upset (SEU) is presented. Placing a resistive element into a feedback loop of the NCL circuit may harden the NCL circuit. A bypass element may be placed in parallel with the resistive element to increase the latching speed of the hardened NCL circuit. Additionally, replacing transistors in an input driver, the feedback loop, and an inverter with transistor stacks, which may include two or more transistors connected in series, may harden the NCL circuit. Further, two NCL gates may be cross-coupled to harden the NCL circuit.

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