Semiconductor device and method of manufacturing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S406000, C257S411000, C257S333000

Reexamination Certificate

active

06953967

ABSTRACT:
A semiconductor device having a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of a plurality of rows and columns. Each of the non-volatile memory devices has: a word gate formed above a semiconductor layer with a gate insulating layer interposed; an impurity layer formed in the semiconductor layer; and control gates in the form of side walls formed along both side surfaces of the word gate. Each of the control gates consists of a first control gate and a second control gate adjacent to each other; the first control gate is formed on a first insulating layer which is a stack of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film; and the second control gate is formed on a second insulating layer formed of a silicon oxide film.

REFERENCES:
patent: 5408115 (1995-04-01), Chang
patent: 5422504 (1995-06-01), Chang et al.
patent: 5494838 (1996-02-01), Chang et al.
patent: 5969383 (1999-10-01), Chang et al.
patent: 6177318 (2001-01-01), Ogura et al.
patent: 6248633 (2001-06-01), Ogura et al.
patent: 6255166 (2001-07-01), Ogura et al.
patent: 6413821 (2002-07-01), Ebina et al.
patent: 6518124 (2003-02-01), Ebina et al.
patent: 2002/0100929 (2002-08-01), Ebina et al.
patent: 2002/0127805 (2002-09-01), Ebina et al.
patent: 2003/0054610 (2003-03-01), Ebina et al.
patent: 2003/0057505 (2003-03-01), Ebina et al.
patent: 2003/0058705 (2003-03-01), Ebina et al.
patent: 2003/0060011 (2003-03-01), Ebina et al.
patent: 2003/0157767 (2003-08-01), Kasuya
patent: 2003/0166320 (2003-09-01), Kasuya
patent: 2003/0166321 (2003-09-01), Kasuya
patent: 2003/0166322 (2003-09-01), Kasuya
patent: 2003/0186505 (2003-10-01), Shibata
patent: 2003/0190805 (2003-10-01), Inoue
patent: 2003/0211691 (2003-11-01), Ueda
patent: A 7-161851 (1995-06-01), None
patent: B1 2978477 (1999-09-01), None
patent: A 2001-156188 (2001-06-01), None
U.S. Appl. No. 10/636,562, filed Aug. 8, 2003, Inoue.
U.S. Appl. No. 10/636,581, filed Aug. 8, 2003, Yamamukai.
U.S. Appl. No. 10/636,582, filed Aug. 8, 2003, Inoue.
U.S. Appl. No. 10/614,985, filed Jul. 9, 2003, Inoue.
U.S. Appl. No. 10/690,025, filed Oct. 22, 2003, Kasuya.
U.S. Appl. No. 10/689,987, filed Oct. 22, 2003, Kasuya.
U.S. Appl. No. 10/689,990, filed Oct. 22, 2003, Kasuya.
Hayashi et al. “Twin MONOS Cell with Dual Control Gates”, 2000 Symposium on VLSI Technology Digest of Technical Papers.
Chang et al. “A New SONOS Memory Using Source-Side Injection for Programming”, IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998, pp 253-255.
Chen et al. A Novel Flash Memory Device with S Plit Gate Source Side Injection and ONO Charge Storage Stack (SPIN), 1997 Symposium on VLSI Technology Digest of Technical Papers, pp 63-64.

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