Method for making large-scale ASIC using pre-engineered long...

Details Method for making large-scale ASIC using pre-engineered long... Method for making large-scale ASIC using pre-engineered long...

2005-09-13

2005-09-13

Callahan, Timothy P. (Department: 2816)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06944842

ABSTRACT:
Optimal routing line segments and associated buffers are pre-engineered for each family of ASIC chips by simulating wires segments of various lengths using distributed resistance and capacitance wire models, and by estimating crosstalk from neighboring line segments. During ASIC design, space is reserved on the ASIC substrate for fabricating the buffers, which are selectively connected by local metal and diffusion structures to form long distance interconnections. Signals are passed from an ASIC circuit structure to a selected long distance interconnection by connecting an output terminal of the ASIC structure either to the input terminal of a buffer located at one end of the interconnection, or by connecting the output terminal directed to a line segment of the interconnection.

REFERENCES:
patent: 5406497 (1995-04-01), Altheimer et al.
patent: 5974245 (1999-10-01), Li et al.
patent: 6242767 (2001-06-01), How et al.
patent: 6601227 (2003-07-01), Trimberger

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