Method for designing interconnects in an LSI

Details Method for designing interconnects in an LSI Method for designing interconnects in an LSI

2005-03-01

2005-03-01

Whitmore, Stacy A. (Department: 2812)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06862716

ABSTRACT:
A method includes the steps of estimating a positive-component average current avg_p and a negative-component average current avg_n of each of terminals of circuit elements; separating the terminals into a positive-node terminal set and a negative-node terminal set by a target branch; calculating Iavg_p and Iavg_n of the target branch as follows:Iavg_p=min⁡(∑m=1M⁢ ⁢am·avg_nm,∑m=1M⁢(1- ⁢am)·avg_pm,),andIavg_n=min⁢(∑m=1M⁢ ⁢am·avg_pm,∑m=1M⁢(1- ⁢am)·avg_nm,),wherein m is the sequential number of the terminals, M is the highest sequential number, am=1 or am=0 depending on the m-th terminal belonging to the positive-node terminal set or negative-node terminal set; selecting a larger value of Iavg_p and Iavg_n as the target branch; and determining the size of the interconnect for the target branch.

REFERENCES:
patent: 6038383 (2000-03-01), Young et al.
patent: 6587991 (2003-07-01), Mbouombouo et al.
patent: 62-120043 (1987-01-01), None
patent: 03-204958 (1991-06-01), None
patent: 04-107953 (1992-09-01), None

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