Memory circuit and method of reading data

Details Memory circuit and method of reading data Memory circuit and method of reading data

2005-04-26

2005-04-26

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S189050, C365S189090

Reexamination Certificate

active

06885601

ABSTRACT:
Malfunction caused by a parasitic capacitance generated between bit lines is prevented. Dummy bit lines are arranged opposite to an address decoder while sandwiching a date storage section. The dummy bit lines are arranged such that the both right and left dummy bit lines having cell transistors sandwich the central dummy bit line having no cell transistor.

REFERENCES:
patent: 5953277 (1999-09-01), Mukunoki et al.
patent: 6018794 (2000-01-01), Kilpatrick
patent: 6381187 (2002-04-01), Lee et al.
patent: 6-259955 (1994-09-01), None
patent: 9-139066 (1997-05-01), None

Affiliated with

Also associated with

Rating

Memory circuit and method of reading data does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory circuit and method of reading data, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory circuit and method of reading data will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3433472