Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2005-04-05

2005-04-05

Phung, Anh (Department: 2824)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S154000, C365S230060

Reexamination Certificate

active

06876573

ABSTRACT:
A semiconductor memory device having a memory array comprising CMOS flip-flop circuit type memory cells, which is capable of improving a noise margin, making a read rate fast and reducing power consumption. In the semiconductor memory device, an operating voltage of the memory cell is set higher than an operating voltage of each of peripheral circuits. Threshold voltages of MOS transistors that constitute the memory cell, are set higher than those of MOS transistors constituting the peripheral circuit. A gate insulting film for the MOS transistors that constitute the memory cell, is formed so as to be regarded as thicker than a gate insulting film for the MOS transistors constituting the peripheral circuit when converted to an insulating film of the same material. Further, a word-line selection level and a bit-line precharge level are set identical to the level of the operating voltage of the peripheral circuit.

REFERENCES:
patent: 5276652 (1994-01-01), Anami
patent: 5677889 (1997-10-01), Haraguchi et al.
patent: 5757702 (1998-05-01), Iwata et al.
patent: 5872737 (1999-02-01), Tsuruda et al.
patent: 5875133 (1999-02-01), Miyashita et al.
patent: 5978299 (1999-11-01), Yamasaki et al.
patent: 6009023 (1999-12-01), Lu et al.
patent: 6046627 (2000-04-01), Itoh et al.
patent: 6316812 (2001-11-01), Nagaoka
patent: 6493282 (2002-12-01), Iida et al.
patent: 20010006476 (2001-07-01), Itoh et al.
patent: 20020027256 (2002-03-01), Ishibashi et al.
patent: 58-161195 (1982-03-01), None
patent: 2-295164 (1989-05-01), None
patent: 3-83289 (1989-08-01), None
patent: 5-120882 (1991-10-01), None
patent: 8-69693 (1994-08-01), None
patent: 9-51042 (1996-02-01), None
patent: 10-242839 (1997-02-01), None
patent: 2001-15704 (2001-01-01), None
patent: WO 9738444 (1997-04-01), None
Takakuni Douseki and Shin-ichiro Mutoh, “Static-Noise Margin Analysis for a Scaled-Down CMOS Memory Cell”, Journal of Institute of Electronics Information and Communication Engineers C-11, (Jul. 1992), vol. J75-c-11 No. 7, pp. 350-361.
T. Inukai, M. Takamiya, K. Nose, H. Kawaguchi, T. Hiramoto and T. Sakurai, “Boosted Gate MOS (BGMOS): Device/Circuit Cooperation Scheme to Achieve Leakage-Free Giga-Scale Integration”, IEEE 2000 Custom Integrated Circuits Conference, pp. 409-412.

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