High performance FET with elevated source/drain region

Details High performance FET with elevated source/drain region High performance FET with elevated source/drain region

2005-03-08

2005-03-08

Smith, Matthew (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S336000, C257S347000, C257S352000, C257S368000, C257S369000, C257S371000, C257S382000, C257S374000, C257S412000, C438S139000, C438S183000, C438S327000, C438S149000, C438S479000, C438S517000

Reexamination Certificate

active

06864540

ABSTRACT:
The invention includes a field effect transistor (FET) on an insulator layer, and integrated circuit (IC) on SOI chip including the FETs and a method of forming the IC. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.

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