Interconnect arrangement and method for fabricating an...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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C257S751000, C257S758000, C257S759000, C257S760000

Reexamination Certificate

active

06888244

ABSTRACT:
An interconnect arrangement (100) has a first layer (101), a first layer surface (102), thereon at least two interconnects (104) having a second layer surface (105) essentially parallel to the first layer surface (102), thereon a respective second layer (106) for each interconnect (104), the second layers (106) of adjacent interconnects covering regions between the adjacent interconnects (104), and thereon a third layer (107), which completely closes off the regions between the adjacent interconnects (104) by means of coverage.

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patent: 0 687 004 (1995-12-01), None
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