Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-04-05
2005-04-05
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S700000, C438S702000, C438S703000, C438S712000, C438S723000, C438S724000, C438S725000, C438S736000, C438S737000, C438S738000, C438S743000, C438S744000, C257S760000
Reexamination Certificate
active
06875688
ABSTRACT:
A method for implementing dual damascene processing includes forming a first hardmask layer over an interlevel dielectric layer, and forming a second hardmask layer over the first hardmask layer. A trench pattern is opened within a third hardmask layer formed over the second hardmask. A first etch process is implemented so as to define a via pattern completely through the second hardmask layer and partially through the first hardmask layer, and a second etch process is implemented to transfer the trench pattern and the via pattern into the interlevel dielectric layer.
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R. Kanamura, Y. Ohnka, M. Fukasawa, K. Tabuchi, K. Nagahata, S. Shibaki, M. Maramatsu, H. Miyajima, T. Usul, A. Kajita, H. Shibata, and S. Kadomura; Integration of Cu/low-k Dual-Damascene Interconnects with a Porous PAE/SIOC Hybrid Structure for 65am-node High Performance eDram 2003 Symposium on VLSI Tech. pp. 107-108.
America William G.
Kumar Kaushik A.
Cantor & Colburn LLP
Cioffi James J.
International Business Machines - Corporation
Keshavan B. V.
Smith Matthew
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