Electrical computers and digital data processing systems: input/ – Access arbitrating
Reexamination Certificate
2005-09-20
2005-09-20
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Access arbitrating
C710S107000, C710S112000, C710S113000, C710S309000, C710S036000, C710S311000, C710S241000
Reexamination Certificate
active
06948019
ABSTRACT:
A slave device on a data bus has a register that stores a non-queued split master vector containing bits identifying whether a transaction with corresponding master devices have been split. An input gate is responsive to the status of the slave device and to receipt of a command from a master device when the slave device status is busy to set a bit in the non-queued split master vector identifying that the transaction with the corresponding master device is split. An output gate is responsive to a not busy status of the slave device to output the non-queued split master vector to the arbiter to re-arbitrate use of the data bus among the previously-split non-queued master devices.
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Moss Robert W.
Sluiter David O.
Stuber Russell B.
Auve Glenn A.
LSI Logic Corporation
Mason Donna K.
Westman Champlin & Kelly
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