UART automatic half-duplex direction control with...

Details UART automatic half-duplex direction control with... UART automatic half-duplex direction control with...

2005-03-08

2005-03-08

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S053000, C710S058000, C455S073000

Reexamination Certificate

active

06865626

ABSTRACT:
A UART with a FIFO buffer is provided. A circuit detects a last word transmitted from the FIFO buffer. A transmitter empty circuit generates a transmitter empty signal (RTS) when the last word transmitted from the FIFO buffer is detected. A delay circuit delays generation of the RTS signal for a programmable time delay. The time delay via a register that is programmable by the user. The invention thus provides the programmable delay on the same chip as the UART.

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Anon, “PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs”, Jun. 1995, pp. 1-22, National Semiconductor Corp., USA XP002264776, retrieved from the Internet: www.national.com/ds/PC/PC16550D.pdf.
Anon, “PC16550D Dual Universal Asynchronous Receiver/Transmitter with FIFOs”, Jun. 1995, pp. 1-22, National Semiconductor Corp., USA-XP002264777, retrieved from the Internet: www.national.com/ds/PC/PC16552D.pdf.

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