Corrected mask pattern verification apparatus and corrected...

Details Corrected mask pattern verification apparatus and corrected... Corrected mask pattern verification apparatus and corrected...

2005-05-31

2005-05-31

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C430S005000, C430S030000

Reexamination Certificate

active

06901569

ABSTRACT:
A corrected mask pattern verification apparatus includes a graphic operation section for generating differential mask pattern data based on design mask pattern and corrected mask pattern; a graphic reduction-enlargement operation section for reducing the differential mask pattern data and enlarging the reduced differential mask pattern data, and generating graphic reduction-enlargement operation data; and an area comparison operation section for calculating an area of a differential mask pattern represented by the differential mask pattern data and comparing the calculated area with a prescribed area, and generating area comparison operation data indicating an area comparison operation result.

REFERENCES:
patent: 6077310 (2000-06-01), Yamamoto et al.
patent: 6440619 (2002-08-01), Feldman
patent: 6665857 (2003-12-01), Ayres
patent: 6704921 (2004-03-01), Liu
patent: 6821689 (2004-11-01), Pierrat
patent: 11-174659 (1999-07-01), None

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