Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-01-04
2005-01-04
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S014000, C703S017000, C709S241000, C709S241000, C709S241000, C710S006000, C710S010000, C710S014000, C710S018000, C712S003000, C712S013000, C712S201000
Reexamination Certificate
active
06839889
ABSTRACT:
A method of implementing a scaleable architecture for a communications system is disclosed, based on minimizing a total gate count for the communications system to reduce cost, complexity, etc. The method considers the requirements of particular communications transmission process that is dividable into individual transmission tasks. A computational complexity for each of said N individual transmission tasks respectively, said computational complexity being based on a number of instructions per second (MIPs) required by a computational circuit to perform each of said N individual transmission tasks; a number of gates and/or transistors required to implement each of individual transmission task using a hardware based or software based computing circuit, etc. After determining an effective number of MIPs acheivable by such circuits, the N tasks are allocated in a gate efficient manner for a final design architecture, or for a working implementation in the field. A system constructed in this fashion is highly gate efficient and cost effective, so that a multiport system can be put on single SOC integrated circuit.
REFERENCES:
patent: 5115451 (1992-05-01), Furlong
patent: 5355508 (1994-10-01), Kan
patent: 5404469 (1995-04-01), Chung et al.
patent: 5442789 (1995-08-01), Baker et al.
patent: 5524244 (1996-06-01), Robinson et al.
patent: 5537601 (1996-07-01), Kimura et al.
patent: 5590323 (1996-12-01), Kartalopoulos
patent: 5687325 (1997-11-01), Chang
patent: 5696759 (1997-12-01), Tomonaga et al.
patent: 5732224 (1998-03-01), Gulick et al.
patent: 5768598 (1998-06-01), Marisetty et al.
patent: 5794067 (1998-08-01), Kadowaki
patent: 5805850 (1998-09-01), Luick
patent: 5815206 (1998-09-01), Malladi et al.
patent: 5818532 (1998-10-01), Malladi et al.
patent: 5854754 (1998-12-01), Cabrera et al.
patent: 5870310 (1999-02-01), Malladi
patent: 5890009 (1999-03-01), Luick et al.
patent: 5920561 (1999-07-01), Daniel et al.
patent: 5933447 (1999-08-01), Tran et al.
patent: 5977997 (1999-11-01), Vainsencher
patent: 5990958 (1999-11-01), Bheda et al.
patent: 6016539 (2000-01-01), Sollars
patent: 6023753 (2000-02-01), Pechanek et al.
patent: 6081783 (2000-06-01), Divine et al.
patent: 6084881 (2000-07-01), Fosmark et al.
patent: 6088785 (2000-07-01), Hudson et al.
patent: 6101592 (2000-08-01), Pechanek et al.
patent: 6122703 (2000-09-01), Nasserbakht
patent: 6128307 (2000-10-01), Brown
patent: 6131114 (2000-10-01), Guezou et al.
patent: 6134605 (2000-10-01), Hudson et al.
patent: 6151668 (2000-11-01), Pechanek et al.
patent: 6157051 (2000-12-01), Allsup
patent: 6167501 (2000-12-01), Barry et al.
patent: 6167502 (2000-12-01), Pechanek et al.
patent: 6173389 (2001-01-01), Pechanek et al.
patent: 6175589 (2001-01-01), Cummings
patent: 6182206 (2001-01-01), Baxter
patent: 6192073 (2001-02-01), Reader et al.
patent: 6338130 (2002-01-01), Sinibaldi et al.
patent: 6570912 (2003-05-01), Mirfakhraei
patent: 20030004697 (2003-01-01), Ferris
patent: 1059785 (2000-12-01), None
patent: 9900739 (1999-01-01), None
patent: 9959078 (1999-11-01), None
patent: 0010281 (2000-02-01), None
patent: 0010297 (2000-02-01), None
patent: 0116777 (2000-03-01), None
patent: 0019311 (2000-04-01), None
patent: 0025250 (2000-05-01), None
patent: 0069084 (2000-11-01), None
patent: 0069192 (2000-11-01), None
patent: 0113590 (2001-02-01), None
patent: 0122235 (2001-03-01), None
patent: 0124030 (2001-04-01), None
patent: 0144964 (2001-06-01), None
patent: 0150624 (2001-07-01), None
patent: 0155864 (2001-08-01), None
patent: 0155917 (2001-08-01), None
NN87055445, “Scheme to Route Transaction Groups in Multi-System Data”, IBM Technical Disclosure Bulletin, vol. 29, No. 1 May 1987, pp. 5445-5449 (8 pages).*
Schneiderman, “Application of ATM traffic analysis techniques in the field of digital signal processing”, Proceedings of the 1997 South African Symposium on Communications and Signal Processing, Sep. 10, 1997, pp. 137-140.*
Murphy et al., “Real-Time MPEG-1 audio coding and decoding on DSP chip”, IEEE Transactions on Consumer Electronics, vol. 43, No. 1, Feb. 1997, pp. 40-47.*
Kumar N. Ganapathy and Benjamin W. Wah,Designing a Coprocessor for Recurrent Computations, In Proceedings of the 5th IEEE Symposium on Parallel and Distributed Processing, pp. 806-813, Dec. 1993.
J. G. Eldredge and B. L. Hutchings,Run-time reconfiguration: A method for enhancing the functional density of SRAM-based FPGAs, Journal of VLSI Signal Processing, 17 pages, 1996.
M. J. Wirthlin and B. L. Hutchings,Sequencing run-time reconfigured hardware with software, In FPGA'96 1996 ACM Fourth International Symposium on Field Programmable Gate Arrays, pp. 122-128, New York, NY, Feb. 1996. ACM.
T. Miyamori and K. Olukotun,A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications, in Proc. IEEE Symp. on FPGAs for Custom Computing Machines, Napa Valley, California, 1998, pp. 2-11.
D. Scherrer and H. Eberle,A Scalable Real-time Signal Processor for Object-oriented Data Flow Applications, PDCS-98 11th Int. Conf. on Parallel and Distributed Computing Systems, Chicago, Sep. 2-4, 1998, pp. 183-189.
K. Compton and S. Hauck,Configurable Computing: A Survey of Systems and Software, Northwestern University, Dept. of ECE Technical Report, 1999, 39 pages.
H.J. Broersma, N. Bruin, J.L. Hurink, L.E. Meester, S.S. op de Beek and J.H. Westhuis,Throughput of ADSL modems, Memorandum No. 1482, ISSN 0169-2690, pp. 1-17.
Paul Graham and Brent Nelson,Reconfigurable Processors for High-Performance, Embedded Digital SIgnal Processing, in Proceedings of the Ninth International Workshop on Field Programmable Logic and Applications, Aug. 1999, 10 pages.
O. Diessel and G. Wigley,Opportunities for Operating Systems Research in Reconfigurable Computing, Technical report ACRC-99-018, Advanced Computing Research Centre, School of Computer and Information Science, University of South Australia, Aug., 1999, pp. 1-12.
S.Köhler, S.Sawitzki, R.G.Spallek,Digital Signal Processors for Multimedia Applications, in Proceedings of the 4th WorldMulticonference on Systemics, Cybernetics and Informatics and the 6th International Conference on Information Systems, Analysis and Synthesis (SCI/ISAS 2000), vol. VI, Image Acoustic, SPeech and Signal Processing: part II, pp. 107-112, International Institute of Informatics an d Systemics, 2000.
Stephan Wong, SOrin Cotofana, Stamatis Vassiliadis,Multimedia Enhanced General-Purpose Processors, IEEE International Conference on Multimedia and Expo (III) 2000: 1493-1496.
Russell Tessier and Wayne Burleson,Reconfigurable Computing for Digital Signal Processing: A Survey,Department of Electrical and Computer Engineering, University of Massachusetts, Apr. 12, 2000, pp. 1-23.
Brian R. Wiese and Jacky S. Chow,Programmable Implementations of xDSL Transceiver Systems, IEEE Communications, May 2000, pp. 114-119.
Finnegan Henderson Farabow Garrett & Dunner
Kik Phallaka
Realtek Semiconductor Corp.
LandOfFree
Mixed hardware/software architecture and method for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Mixed hardware/software architecture and method for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mixed hardware/software architecture and method for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3426226