Pre-steering register renamed instructions to execution unit...

Details Pre-steering register renamed instructions to execution unit... Pre-steering register renamed instructions to execution unit...

2005-09-13

2005-09-13

Kim, Kenneth S. (Department: 2111)

Electrical computers and digital processing systems: processing

Instruction issuing

Simultaneous issuance of multiple instructions

C711S129000, C712S216000

Reexamination Certificate

active

06944750

ABSTRACT:
The present invention is directed to a system and method for implementing a pre-steered instruction cache. The hardware logic that normally steers instructions to specific execution units just prior to execution is moved before the pre-steered instruction cache, so that instructions are pre-steered into that cache. In other words, the instructions can be moved into the instruction cache in such a manner that they are organized in the cache depending on the execution unit(s) to which they will be transmitted. This is done so that an instruction can leave the pre-steered instruction cache and enter the execution unit that can execute it with either minimum or no steering logic involvement. The cache lines of the pre-steered instruction cache are organized into bins such that each bin corresponds to either a single execution unit or a cluster of execution units.

REFERENCES:
patent: 5442760 (1995-08-01), Rustad et al.
patent: 5471593 (1995-11-01), Branigin
patent: 5790822 (1998-08-01), Sheaffer et al.
patent: 5978899 (1999-11-01), Ginosar et al.
patent: 6219780 (2001-04-01), Lipasti
patent: 6351802 (2002-02-01), Sheaffer
patent: 6519683 (2003-02-01), Samra et al.

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