Method and apparatus for optimizing the timing of integrated...

Details Method and apparatus for optimizing the timing of integrated... Method and apparatus for optimizing the timing of integrated...

2005-03-15

2005-03-15

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06868535

ABSTRACT:
Integrated circuits are designed having optimal signal timing between and among cells. A set of identities are generated corresponding to logic operations and to library cells in technology basis. A resynthesis window is created for the identities having less than a predetermined depth of critical variables. Logic equations of the resynthesis window are transformed using the identities, and the resynthesized window area is optimized.

REFERENCES:
patent: 6591407 (2003-07-01), Kaufman et al.

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