Integrated circuit and method of reading data from a memory...

Details Integrated circuit and method of reading data from a memory... Integrated circuit and method of reading data from a memory...

2005-01-25

2005-01-25

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

C365S189050, C365S189120

Reexamination Certificate

active

06847558

ABSTRACT:
A blockRAM based FIFO utilizes the blockRAM components to implement a one-cycle latency read FIFO. This FIFO implementation, while utilizing blockRAM, provides fast clock to out times by registering all data in a register prior to presenting it to the user. Because this implementation transparently registers the data, the user interface remains identical to conventional FIFO implementations, while solving the slow clock-to-out time associated with blockRAM based FIFOs. A blockRAM based zero-cycle latency read FIFO is also described.

REFERENCES:
patent: 6519689 (2003-02-01), Manning
patent: 6603706 (2003-08-01), Nystuen et al.

Affiliated with

Also associated with

Rating

Integrated circuit and method of reading data from a memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit and method of reading data from a memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit and method of reading data from a memory... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3423268