Semiconductor package and fabrication method thereof

Details Semiconductor package and fabrication method thereof Semiconductor package and fabrication method thereof

2005-05-10

2005-05-10

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Ball or nail head type contact, lead, or bond

C257S666000, C257S690000, C257S701000, C257S738000, C257S778000, C257S786000

Reexamination Certificate

active

06891273

ABSTRACT:
A semiconductor package and a fabrication method thereof are provided in which a chip is mounted on a substrate, and a dielectric layer is applied over the substrate and chip, with bond fingers formed on the substrate and electric contacts formed on the chip being exposed outside. A metal layer is formed over the dielectric layer and the exposed bond fingers and electric contacts, and patterned to form a plurality of conductive traces that electrically connect the electric contacts of the chip to the bond fingers of the substrate. The conductive traces replace conventional wire bonding technology and thus eliminate the occurrence of wire sweep or short circuits in fabrication processes. Therefore, a low profile chip with a reduced pitch between adjacent electric contacts can be used without being limited to feasibility of the wire bonding technology.

REFERENCES:
patent: 5581122 (1996-12-01), Chao et al.
patent: 6396136 (2002-05-01), Kalidas et al.
patent: 6506632 (2003-01-01), Cheng et al.
patent: 20020020898 (2002-02-01), Vu et al.
patent: 20030134455 (2003-07-01), Cheng et al.

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