Semiconductor memory device equipped with control circuit...

Details Semiconductor memory device equipped with control circuit... Semiconductor memory device equipped with control circuit...

Filed on

2005-04-19

Date issued

2005-04-19

Examiner

Nguyen, Tan T. (Department: 2818)

Patent Class

Static information storage and retrieval

SubClass

Read/write circuit

SubSubClass

Testing

Other Related Categories

C365S194000, C365S195000, C365S222000

Type

Reexamination Certificate

Status

active

Patent number

06882586

Description

ABSTRACT:
A semiconductor memory device is provided with a memory cell array including memory cells being arranged in a shape of matrix and requiring a refresh operation. In the semiconductor memory device, a control circuit controls a timing of the refresh operation in accordance with an internal signal independently of an external signal and controlling the memory cell array in a non-normal operation mode different from a normal operation mode for writing data into the memory cell array and reading out data from the memory cell array. The control circuit starts the non-normal operation mode in response to a sequence of entry into the non-normal operation mode based on a predetermined first command signal, sets the non-normal operation mode in response to a sequence of setting the non-normal operation mode based on a predetermined second command signal, and thereafter, executes operation of the corresponding non-normal operation mode which is set.

REFERENCES:
patent: 5925141 (1999-07-01), Ariki
patent: 6522589 (2003-02-01), Miyakawa et al.
patent: 6707736 (2004-03-01), Miyakawa et al.
patent: 6741511 (2004-05-01), Nakao
U.S. Appl. No. 09/973,894, filed Oct. 11, 2001, Sato et al., U.S. Pat 6,795,943.
U.S. Appl. No. 10/120,445, filed Apr. 12, 2002, Makabe et al., U.S. Pat 6,707,735.

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