Multi-ported memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C711S100000, C711S131000, C711S154000

Reexamination Certificate

active

06877071

ABSTRACT:
In accordance with an embodiment of the invention, a semiconductor memory includes a number of data ports each having a predetermined number of data bits. The memory further has a number of memory macros each including at least one memory array having rows and columns of memory cells. Each memory macro further includes a plurality of internal data connection points directly connected to external terminals to transfer data to or from the at least one memory array. The internal data connection points correspond in number to the number of the data ports, and the internal data connection points in the memory macros together form the plurality of data ports.

REFERENCES:
patent: 5717646 (1998-02-01), Kyi
patent: 5815456 (1998-09-01), Rao
patent: 5990564 (1999-11-01), Degani et al.
patent: 6075711 (2000-06-01), Brown et al.
patent: 6141287 (2000-10-01), Mattausch
patent: 6189073 (2001-02-01), Pawlowski
patent: 6212607 (2001-04-01), Miller et al.
patent: 6233659 (2001-05-01), Cohen et al.
patent: 6329712 (2001-12-01), Akram et al.
patent: 6335899 (2002-01-01), Jung
patent: 6360344 (2002-03-01), Khoche et al.
patent: 6400575 (2002-06-01), Brown et al.
patent: 20020058395 (2002-05-01), Akram et al.
patent: 20030076731 (2003-04-01), Terada
“10Gb/s 3.3V Quadport™ DSE Family,” available at http://www.cypress.com, Cypress Semiconductor Corporation, 3901 North First Street San Jose, CA USA (2002).
“3.3V 64K/128K/256K x36 and 128/256K x 18 Synchronous Dual-port RAM,” available at http://www.cypress.com, Cypress Semiconductor Corporation, 3901 North First Street San Jose, CA USA (2002).
“Introducing the Cypress Quadport™ Switch,” (CY7CO4308V), available at http://www.cypress.com, Cypress Semiconductor Corporation, 3901 North First Street San Jose, CA USA (2002).
“Low Power Clock Distribution,”Low Power Design Methodologies, Jan M. Rabaey and Massoud Pedram eds., Kluwer Academic Publishers, Norwell, MA USA, pp. 119-125 (1996).
“Using Quadport™ DSE Switching Applications,” available at http://www.cypress.com, Cypress Semiconductor Corporation, 3901 North First Street San Jose, CA USA (2002).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Multi-ported memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-ported memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-ported memory will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3419403

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.