Methods and structure for using a memory model for efficient...

Details Methods and structure for using a memory model for efficient... Methods and structure for using a memory model for efficient...

2005-05-10

2005-05-10

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S209000, C711S005000

Reexamination Certificate

active

06892289

ABSTRACT:
In a system having multiple master devices coupled to a shared resource, methods and structure for a state machine based memory model associated with each bank of memory to provide an arbiter with information for generating optimal sequences of memory commands to enable improved memory subsystem bandwidth utilization. The memory model corresponding to each bank of memory emulates the latencies involved with switching of active rows or pages in the corresponding bank. Signals generated by the memory model are applied to the arbiter to enable the arbiter to efficiently determine the optimal timing for generation of memory access commands corresponding to that bank.

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