Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2005-01-18
2005-01-18
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S021000
Reexamination Certificate
active
06844754
ABSTRACT:
In a memory system having a data bus transferring data in either direction, highly reliable data transfer is provided regardless of the direction in which data is transferred. The signal lines of a data bus (12) bidirectionally transfer data. That is to say, during data write operations to a DIMM, the signal lines transfer data from a memory controller (10) to the DIMM, and during data read operations, they transfer data from the DIMM to the memory controller (10). The signal lines have, as terminating resistors, terminating variable resistors (VRt) whose impedance is controlled by the memory controller (10). During data write operations to the DIMM, the memory controller (10) sets the impedance of each terminating variable resistor (VRt) at a value suitable for writing, and during data read operations, it sets the impedance of each terminating variable resistor (VRt) at a value suitable for reading.
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Cho James H.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Renesas Technology Corp.
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