Systems and methods for memory read response latency detection

Details Systems and methods for memory read response latency detection Systems and methods for memory read response latency detection

2005-09-06

2005-09-06

Elmore, Stephen (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S115000, C711S147000, C711S154000, C365S191000, C365S194000

Reexamination Certificate

active

06941433

ABSTRACT:
A system for determining a memory read latency includes a memory, a memory read circuit, and a latency detector. An identifiable pattern of data is written to at least one location in the memory, and a read request and the address of the identified pattern are sent to the memory. The latency detector determines a read latency period based on detecting the identifiable pattern of data.

REFERENCES:
patent: 5655113 (1997-08-01), Leung et al.
patent: 5809517 (1998-09-01), Shimura
patent: 5917760 (1999-06-01), Millar
patent: 6067606 (2000-05-01), Holscher et al.
patent: 6330645 (2001-12-01), Harriman
patent: 6445624 (2002-09-01), Janzen et al.
patent: 2002/0184461 (2002-12-01), Zumkehr
patent: 2002/0188816 (2002-12-01), Johnson et al.

Affiliated with

Also associated with

Rating

Systems and methods for memory read response latency detection does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Systems and methods for memory read response latency detection, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Systems and methods for memory read response latency detection will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3413952