Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2005-01-11
2005-01-11
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C438S692000
Reexamination Certificate
active
06841479
ABSTRACT:
The invention provides a method of reducing in-trench smearing during polishing. The method comprises providing a substrate comprising a first layer comprising an insulating material, a second layer comprising a filling material, and a plurality of field and trench regions. A polymeric material is infiltrated over the substrate, wherein the polymeric material fills the trench regions and covers the field regions. The polymeric material optionally is removed from the field regions, followed by baking of the substrate such that the polymeric material in the trench regions becomes recessed below the insulating material of the field regions. The substrate is then subjected to a temperature of about 100° C. or more for about 30 minutes or longer, such that during polishing of the substrate, smearing of the filling material in the trench regions is reduced as compared to polishing of the substrate under the same conditions except for subjecting the substrate to the temperature of about 100° C. or more for about 30 minutes or longer. When desirable, a layer of additional material can be deposited over the polymeric material such that it forms a layer over the polymeric material in the trench regions and the filling material in the field regions. The substrate is then polished to obtain a substantially planar surface.
REFERENCES:
patent: 4268951 (1981-05-01), Elliott et al.
patent: 4546534 (1985-10-01), Nicholas
patent: 5891804 (1999-04-01), Havemann et al.
patent: 5976970 (1999-11-01), Dalal et al.
patent: 6010962 (2000-01-01), Liu et al.
patent: 6043146 (2000-03-01), Watanabe et al.
patent: 6124164 (2000-09-01), Al-Shareef et al.
patent: 6150690 (2000-11-01), Ishibashi et al.
patent: 6153525 (2000-11-01), Hendricks et al.
patent: 6159818 (2000-12-01), Durcan et al.
patent: 6271083 (2001-08-01), Lou
patent: 6278153 (2001-08-01), Kikuchi et al.
patent: 6372616 (2002-04-01), Yoo et al.
patent: 1083597 (2001-03-01), None
patent: 1 083 597 (2001-03-01), None
Database WPI, Section Ch., Week 200140, Derwent Publications, Ltd., London, GB; AN 2001-380044 XP002214080 & TW 417 293 A Worldwide Semiconductor Mfg. Corp ), Jan. 1, 2001 abstract.
Patent Abstracts of Japan, vol. 2000, No. 11, Jan. 3, 2001, & JP 2000-223362 A (NEC Corp.), Aug. 11, 2000 abstract.
Cherian Isaac K.
Feeney Paul M.
Moeggenborg Kevin J.
Cabot Microelectronics Corporation
Chen Kin-Chan
Lanning Robert M.
LandOfFree
Method of reducing in-trench smearing during polishing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of reducing in-trench smearing during polishing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of reducing in-trench smearing during polishing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3411105