Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-05-17
2005-05-17
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06895567
ABSTRACT:
The present invention introduces several methods for laying out integrated circuit designs that use gridless non Manhattan routing to connect the integrated circuit components. In one embodiment, the non Manhattan routed integrated circuit designs are laid out by creating an initial route and then compacting the design down. In another embodiment, gridless non Manhattan integrated circuits are laid out by adapting a gridless Manhattan routing system into a gridless non Manhattan routing system by rotating a plane of a tile based maze router.
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Caldwell Andrew
Teig Steven
Cadence Design Systems Inc.
Rossoshek Helen
Stattler Johansen & Adeli LLP
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