Semiconductor device with multi-bank DRAM and cache memory

Details Semiconductor device with multi-bank DRAM and cache memory Semiconductor device with multi-bank DRAM and cache memory

2005-01-25

2005-01-25

Moazzami, Nasser (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S005000, C711S105000, C711S106000, C711S118000, C711S119000, C711S120000, C711S123000, C711S125000, C711S126000, C711S128000, C711S141000, C711S143000, C711S144000

Reexamination Certificate

active

06848035

ABSTRACT:
A semiconductor device is designed to hide refresh operations even when the data width of a cache line differs from that of the external data bus in a memory that uses a cache memory and a DRAM with a plurality of banks. The semiconductor device includes a plurality of memory banks BANK0to BANK127, each having a plurality of memory cells, as well as a cache memory CACHEMEM used to retain information read from the plurality of memory banks. The cache memory CACHEMEM includes a plurality of entries, each having a data memory DATAMEM and a tag memory TAGMEM. The data memory DATAMEM has a plurality of sub lines DATA0to DATA3and the tag memory TAGMEM has a plurality of valid bits V0to V3and a plurality of dirty bits D0to D3.

REFERENCES:
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patent: 6028804 (2000-02-01), Leung et al.
patent: 6075740 (2000-06-01), Leung et al.
patent: 6381671 (2002-04-01), Ayukawa et al.
patent: 6415353 (2002-07-01), Leung

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