Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-03-22
2005-03-22
Whitmore, Stacy A. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C438S030000, C216S023000
Reexamination Certificate
active
06871339
ABSTRACT:
In a method of manufacturing a device which includes processes in which a plurality of unit regions (first bits D1and second bits D2) are established upon a substrate in the form of a lattice, and in which liquid drops are discharged by an ink device in each unit region, when a first bitmap which is made up from a plurality of the first bits D1and a second bitmap which is made up from a plurality of the second bits D2whose size is different from that of the first bits D1have been established, the highest common divisor of the size of the first bits D1and the size of the second bits D2is calculated, this highest common divisor is taken as the size of third bits D3, the first bitmap and the second bitmap are re-set to the third bits, and the liquid drops are discharged in positions regulated by the third bitmap.
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patent: 6156669 (2000-12-01), Knappenberger
patent: 6503831 (2003-01-01), Speakman
patent: 6531329 (2003-03-01), Asakura et al.
patent: 6566154 (2003-05-01), Yamamoto
patent: 6710843 (2004-03-01), Choo et al.
patent: 6713389 (2004-03-01), Speakman
patent: A 11-274671 (1999-10-01), None
patent: A 2000-216330 (2000-08-01), None
Seiko Epson Corporation
Whitmore Stacy A.
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