Register-file bit-read method and apparatus

Details Register-file bit-read method and apparatus Register-file bit-read method and apparatus

2005-07-05

2005-07-05

Chang, Daniel D. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

C326S062000, C326S040000, C365S189020, C365S189110

Reexamination Certificate

active

06914450

ABSTRACT:
A register-file bit read apparatus includes a decoder operable to receive a number of address-bit signals and responsively assert a select signal on one of M select lines. Each select line corresponds to a respective one of M register-file cells. The apparatus also includes a multiplexer having Q output nodes and M selectors. Each selector is coupled to one of the select lines and that select line's corresponding register-file cell. The selectors are in Q groups, each coupled to a respective one of the multiplexer's output nodes. The apparatus also includes an output logic gate having Q inputs, coupled to respective ones of the multiplexer output nodes. The multiplexer includes Q pull-ups, each of which is coupled to a respective one of the multiplexer output nodes and is operable to drive its multiplexer output node responsive to one of the address-bit signals.

REFERENCES:
patent: 5583450 (1996-12-01), Trimberger et al.
patent: 6373279 (2002-04-01), Bauer et al.
patent: 6445209 (2002-09-01), Young et al.
patent: 6529040 (2003-03-01), Carberry et al.
patent: 6621296 (2003-09-01), Carberry et al.
patent: 2003/0071653 (2003-04-01), Carberry et al.

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