Creation of subresolution features via flow characteristics

Details Creation of subresolution features via flow characteristics Creation of subresolution features via flow characteristics

2005-01-25

2005-01-25

Nguyen, Thanh (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S619000, C438S637000, C438S421000, C438S422000

Reexamination Certificate

active

06846736

ABSTRACT:
An integrated circuit having at least one electrical interconnect for connecting at least two components and a process for forming the same are disclosed. At least two opposing, contoured, merging dielectric surfaces define at least one elongated passageway which has at least one opening. A conductive material then substantially fills the at least one opening and at least one elongated passageway to form at least one electrical interconnect guided by the at least one elongated passageway and extended through the layer of dielectric material along the length to electrically connect at least two of the components of the integrated circuit.

REFERENCES:
patent: 2929753 (1960-03-01), Noyce
patent: 3837907 (1974-09-01), Berglund et al.
patent: 3873373 (1975-03-01), Hill
patent: 3985597 (1976-10-01), Zielinski
patent: 4149301 (1979-04-01), Cook
patent: 4411708 (1983-10-01), Winhan
patent: 4571819 (1986-02-01), Rogers et al.
patent: 4721689 (1988-01-01), Chaloux, Jr. et al.
patent: 4807016 (1989-02-01), Douglas
patent: 4839306 (1989-06-01), Wakamatsu
patent: 4839715 (1989-06-01), Gajda et al.
patent: 4840923 (1989-06-01), Flagello et al.
patent: 4920403 (1990-04-01), Chow et al.
patent: 5001079 (1991-03-01), van Laarhoven et al.
patent: 5004704 (1991-04-01), Maeda et al.
patent: 5010039 (1991-04-01), Ku et al.
patent: 5136358 (1992-08-01), Sakai et al.
patent: 5166101 (1992-11-01), Lee et al.
patent: 5225372 (1993-07-01), Savkar et al.
patent: 5275972 (1994-01-01), Ogawa et al.
patent: 5278103 (1994-01-01), Mallon et al.
patent: 5648175 (1997-07-01), Russell et al.
patent: 5656556 (1997-08-01), Yang
patent: 5677241 (1997-10-01), Manning
patent: 5691565 (1997-11-01), Manning
patent: 5750415 (1998-05-01), Gnade et al.
patent: 5814555 (1998-09-01), Bandyopadhyay et al.
patent: 5880018 (1999-03-01), Boeck et al.
patent: 5880797 (1999-03-01), Yamada et al.
patent: 6030860 (2000-02-01), Gardner et al.
patent: 6031286 (2000-02-01), Levine et al.
patent: 6107205 (2000-08-01), Yu
patent: 6130151 (2000-10-01), Lin et al.
patent: 6165890 (2000-12-01), Kohl et al.
patent: 6365489 (2002-04-01), Ireland
patent: 6376330 (2002-04-01), Fulford, et al.
patent: 6479378 (2002-11-01), Ireland
patent: 1-296641 (1989-11-01), None
F. S. Becker S. Rohl,Low Pressure Deposition of Doped SiO2 by Pyrolysis of Tetraethylorthosilicate(TEOS), Solid-State Science and Technology, Nov. 1987, vol. 134, No. 11, pp. 2923-2931.
B.L. Chin, E.P. van de Ven,Plasma TEOS Process for Interlayer Dielectric Applications,Solid State Technology, Apr. 1988, pp. 119-122.

Affiliated with

Also associated with

Rating

Creation of subresolution features via flow characteristics does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Creation of subresolution features via flow characteristics, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Creation of subresolution features via flow characteristics will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3406404