Co-prime division prescaler and frequency synthesizer

Details Co-prime division prescaler and frequency synthesizer Co-prime division prescaler and frequency synthesizer

2005-01-18

2005-01-18

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

C377S048000

Reexamination Certificate

active

06845139

ABSTRACT:
A system may include a control unit and a dual modulus prescaler. The control unit may generate a modulus control signal. The dual modulus prescaler may be configured to divide the frequency of an input signal by Q when the modulus control signal has a first value and to divide the frequency of the input signal by (Q+V) when the modulus control signal has a second value. Q is an irreducible fraction. The sum (Q+V) may be an integer or a fraction. The dual-modulus prescaler includes several clocked storage units (e.g., flip-flops) that are each clocked by a respective one of several equally spaced phases of the input signal. Each clocked storage unit operates in a toggle mode.

REFERENCES:
patent: 6614870 (2003-09-01), Miller
patent: 20020006179 (2002-01-01), Verlinden
patent: 20020033738 (2002-03-01), Sacki et al.

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