Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2005-09-06

2005-09-06

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S154000, C365S230030

Reexamination Certificate

active

06940739

ABSTRACT:
A memory structure/circuit has at least two memory cell arrays connected to each other in a hierarchy. The bit lines of the two or more memory cell arrays are connected by hierarchy switches. The memory cells of one of the arrays can be read out faster than the others by using the hierarchy switches to select one array without selecting the other arrays. So the data that is read with higher frequency can be selectively read out faster if it is stored in the faster access memory array. If the data in the faster access memory cell array includes a copy of the data in the other array, it can be used as a cache memory. A tag array and data array in combination that are connected to another tag array and data array in combination through hierarchy switch connections can provide a cache memory that is direct mapped or set associative, and also full associative. The memory device can be used in a semiconductor data processor having a CPU in which the memory device is connected to the CPU through a bus, wherein both the CPU and the memory device are formed on a single semiconductor substrate. The memory device can also be an off-chip device.

REFERENCES:
patent: 4831591 (1989-05-01), Imazeki et al.
patent: 5473568 (1995-12-01), Okamura
patent: 5499216 (1996-03-01), Yamamoto
patent: 5581503 (1996-12-01), Matsubara et al.
patent: 5668770 (1997-09-01), Itoh et al.
patent: 5943284 (1999-08-01), Mizuno et al.
patent: 6525985 (2003-02-01), Mizuno et al.
patent: 56-061082 (1981-05-01), None
patent: 60-202596 (1985-10-01), None
patent: 1166394 (1989-06-01), None
patent: 3-83289 (1991-04-01), None
patent: 03-286495 (1991-12-01), None
patent: 04-182985 (1992-06-01), None
patent: 07-085676 (1995-03-01), None
patent: 07-114794 (1995-05-01), None
“A 1-V 100 MHz 10-mW Caceh Using a Separated Bit-Line Memory Hierarchy Architecture and Domino Tag Comparators”, H. Mizuno et al, pp. 1-4.
IEEE 1990 Symposium on VLSI Circuits, “A IV Operating 256—Kbit Full CMOS SRAM”, A. Sekiyama et al, pp. 53-54.
1994 IEEE Symposium on Low Power Electronics, “Low-Power Design of Memory Intensive Functions”, D. Lidsky et al, pp. 16-17.

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3405712