Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Recessed oxide by localized oxidation
Reexamination Certificate
2005-01-25
2005-01-25
Hu, Shouxiang (Department: 2811)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Recessed oxide by localized oxidation
C438S022000, C438S200000, C438S237000, C438S451000
Reexamination Certificate
active
06846722
ABSTRACT:
The present disclosure relates to a method for fabricating an image sensor capable of improving dark current characteristics. The method includes: forming sequentially a pad oxide layer and a pad nitride layer on a substrate and selectively removing a portion of the pad oxide layer and a first portion of the pad nitride layer to expose a surface of the substrate on which a field insulation layer will be formed; forming a first ion-implantation region by performing a first ion-implantation process on the exposed surface of the substrate using the remaining pad nitride layer that exists after removal of the first portion of the pad nitride layer as a first mask; performing a thermal oxidation process to form the field insulation layer on the exposed surface of the substrate; removing a second portion of the pad nitride layer so that a side of the remaining pad nitride layer that exists after removal of the second portion of the pad nitride layer is spaced apart from an edge of the field insulation layer by a distance; and forming a second ion-implantation region by performing a second ion-implantation process on the field insulation layer using the remaining pad nitride layer that exists after removal of the second portion of the pad nitride layer as a second mask.
REFERENCES:
patent: 5128274 (1992-07-01), Yabu et al.
patent: 6281533 (2001-08-01), Miyagawa et al.
patent: 6351002 (2002-02-01), Pan
patent: 6417023 (2002-07-01), Suzuki et al.
patent: 6528342 (2003-03-01), Miyagawa et al.
patent: 20010017382 (2001-08-01), Rhodes et al.
patent: 20020117699 (2002-08-01), Francois
patent: 05075043 (1993-03-01), None
patent: 05-283404 (1993-10-01), None
patent: 05283404 (1993-10-01), None
Fujieda et al., “Dependence of Si PN Junction Perimeter Leakage on the Channel-Stop Boron Dose and Interlayer Material” (IEEE Electron Device Letters, vol. 20, No. 8, Aug. 1999, pp. 418-420).
Morris et al., “An Accurate and Efficient Model for Boron Implants Through Thin Oxide Layers into Single-Crystal Silicon” (IEEE Transactions on Semiconductor Manufacturing, vol. 8, No. 4, Nov. 1995, pp. 408-413).
Walter et al., “Dopant Channeling as a Function of Implant Angle for Low Energy Applications” (IEEE, 1999, pp. 126-129).
Son et al., “Blanket Tilt Implanted Shallow Trench Isolation (BTI-STI) Process for Enhanced DRAM Retention Time Characteristics” (IEEE, 1999, pp. 122-124).
Hu Shouxiang
Hynix / Semiconductor Inc.
Marshall & Gerstein & Borun LLP
LandOfFree
Method for isolating a hybrid device in an image sensor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for isolating a hybrid device in an image sensor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for isolating a hybrid device in an image sensor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3404933