General purpose delay logic

Details General purpose delay logic General purpose delay logic

2005-09-27

2005-09-27

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Having logic levels conveyed by signal frequency or phase

C327S276000, C327S277000, C327S284000

Reexamination Certificate

active

06949956

ABSTRACT:
A logic circuit for delaying a signal input thereto a specified number of clock cycles X, wherein X is between 1 and 2Nis described. In one embodiment, the logic circuit comprises a demultiplexer (“DEMUX”) comprising an input for receiving the signal and N outputs; a register array comprising 2Nclocked registers, wherein each of a first N of the clocked registers is connected to one of the N outputs of the DEMUX and wherein data is shifted out of one clocked register to a next clocked register on each clock cycle; and a multiplexer (“MUX”) comprising M inputs, wherein each of the M inputs is connected to one of the clocked registers.

REFERENCES:
patent: 6281728 (2001-08-01), Sung
Bart Vermeulen and Sandeep Kumar Goel, “Design for Debug: Catching Design Errors in Digital Chips”, IEEE Design & Test of Computers; May-Jun. 2002; pp. 37-45.
Affidavit of Richard W. Adkisson, Feb. 17, 2005, 4 pages.

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