Method for applying instructions to microprocessor in test mode

Details Method for applying instructions to microprocessor in test mode Method for applying instructions to microprocessor in test mode

2005-05-10

2005-05-10

Baderman, Scott (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S031000

Reexamination Certificate

active

06892322

ABSTRACT:
A method for applying instructions to a microprocessor during test mode is disclosed. In one embodiment of the present invention, first a test mode is entered, establishing the microprocessor as a slave and a test controller as a master. Then, the test controller fills an instruction queue with instructions to be executed. The instructions originate from a test interface. A memory, such as a program flash, coupled to the microprocessor is bypassed; thus, the microprocessor is forced to execute instructions from the instruction queue. In another embodiment, the test controller transfers to the instruction queue an instruction to be executed in the microprocessor. Then, the instruction causes instructions from a supervisory memory to be executed by the microprocessor. The supervisory memory comprises pre-determined test instructions.

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CYPR-CD00176; “Test Architecture For Microcontroller Providing For a Serial Communication Interface”; Oct. 5, 2001; 09/972,003; W. Snyder.
CYPR-CD00178; “Method For Entering Circuit Test Mode”; Oct. 5, 2001; 09/972,133; W. Snyder.

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