Self-repairing built-in self test for linked list memories

Details Self-repairing built-in self test for linked list memories Self-repairing built-in self test for linked list memories

2005-07-12

2005-07-12

Lam, David (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C365S185090

Reexamination Certificate

active

06917548

ABSTRACT:
A process of repairing defects in linked list memories including selecting one of a group of the linked list memories and an additional memory, as a defect marking memory, detecting faults in rows of the defect marking memory, and storing row addresses having at least one fault in defect address registers. The method detects faults in rows of other linked list memories, where the other linked list memories are the linked list memories other than the defect marking memory, and stores a marking code for each row address of the other linked list memories in the defect marking memory. The defect address registers and the defect marking memory are searched when addresses of the linked list memories are linked and row addresses having a specific marking code skipped in the linking process.

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