Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2005-01-11
2005-01-11
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S006130, C714S006130, C714S710000, C710S068000
Reexamination Certificate
active
06842874
ABSTRACT:
A method and apparatus for identifying defective cells in a memory array includes receiving a request for accessing an address and analyzing the address to determine when the address matches an address stored in a temporary memory array. When the address does not match any address stored in the temporary memory array, a wait instruction is sent to a processor and the address is analyzed to determine which portion of compressed data stored in a map memory array to decompress. The map memory array stores data containing compressed addresses of defective cells in a first memory array. The portion of compressed data is then decompressed to provide expanded data when the address does not match any address stored in the temporary memory array. The expanded data are then written to the temporary memory array, and the expanded data are compared to the address to determine when the address corresponds to an expanded datum of the expanded data.
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Dorsey & Whitney LLP
Lamarre Guy J.
Micro)n Technology, Inc.
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