SRAM system having very lightly doped SRAM load transistors...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S369000, C257S371000, C257S344000, C257S346000, C257S391000, C257S392000, C257S407000, C257S408000, C438S153000, C438S154000, C438S199000, C438S231000, C438S232000, C438S279000, C438S299000

Reexamination Certificate

active

06894356

ABSTRACT:
A static random access memory (SRAM) cell is given increased stability and latch-up immunity by fabricating the PMOS load transistors of the SRAM cell to have a very low drain/source dopant concentration. The drain/source regions of the PMOS load transistors are formed entirely by a P−− blanket implant. The PMOS load transistors are masked during subsequent implant steps, such that the drain/source regions of the PMOS load transistors do not receive additional P-type (or N-type) dopant. The P−− blanket implant results in PMOS load transistors having drain/source regions with dopant concentrations of 1e17 atoms/cm3or less. The dopant concentration of the drain/source regions of the PMOS load transistors is significantly lower than the dopant concentration of lightly doped drain/source regions in PMOS transistors used in peripheral circuitry.

REFERENCES:
patent: 5497023 (1996-03-01), Nakazato et al.
patent: 5589701 (1996-12-01), Baldi
patent: 5668770 (1997-09-01), Itoh et al.
patent: 5780330 (1998-07-01), Choi
patent: 5804477 (1998-09-01), Lien
patent: 6031267 (2000-02-01), Lien
patent: 6191460 (2001-02-01), Choi et al.

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