Interconnect exhibiting reduced parasitic capacitance variation

Details Interconnect exhibiting reduced parasitic capacitance variation Interconnect exhibiting reduced parasitic capacitance variation

2005-03-01

2005-03-01

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06862720

ABSTRACT:
Adjacent metal lines of an interconnect metallization layer exhibit reduced variation in parasitic capacitance due to the presence of an intervening third metal line. The third metal line is electrically linked to one of the adjacent metal lines and is designed to project into the space between the adjacent metal lines, thereby elevating parasitic capacitance while reducing the range of variation of parasitic capacitance over a known range of critical dimensions. Thickness of the interlayer dielectric formed over the adjacent metal lines can be tailored to trigger penetration of the third metal line within a known range of critical dimensions.

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Stanley Wolf, “Silicon Processing for the VLSI ERA ”, vol. 2: Process Integration, 1990, pp. 183-186.

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