Method and apparatus for sampling digital data at a...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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Reexamination Certificate

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06865241

ABSTRACT:
An improved data acquisition system interface provides virtually constant sampling of input signals and provides those signals in a digitized format to a data acquisition unit that may not be able to sample at a constant rate without missing or “losing” some of the samples. The present invention acts as a front end interface that temporarily latches the sampled data, expands the data into multiple parallel signals, then stores the multiple parallel signals in a dual-port FIFO memory unit. Finally, the multiple parallel signals are transferred into the data acquisition unit at a lower frequency, and the transfer operations take place only when the data acquisition unit is ready to accept data. Since the front end misses no sampling intervals (i.e., it always takes a sample according to an extremely constant frequency crystal clock), then the data acquisition unit will be provided with all of these samples without losing any data. The only requirement is that the data throughput of the multiple parallel signals into the data acquisition unit be greater than or equal to the data sampling rate of the original signal at the front end. The present invention can be used with pure digital signals to capture their precise times of logic state transitions, or with serial data signals in which the precise moments of transition can be used to decipher the serial data. Moreover, the interface can be used with analog signals that are digitized using an analog-to-digital converter.

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