Single poly UV-erasable programmable read only memory

Details Single poly UV-erasable programmable read only memory Single poly UV-erasable programmable read only memory

2005-04-19

2005-04-19

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185320

Reexamination Certificate

active

06882574

ABSTRACT:
An erasable programmable read only memory includes two serially connected P-type metal-oxide semiconductor (MOS) transistors, wherein a first P-type MOS transistor acts as select transistor, a gate of the first P-type MOS transistor is coupled to select gate voltage, a first node of the first P-type MOS transistor connected to source line voltage, a second node of the first P-type MOS transistor connected to a first node of a second P-type MOS transistor, wherein a second node of the second P-type MOS transistor is connected to bit line voltage, wherein a gate of the second P-type MOS transistor serves as a floating gate, wherein the erasable programmable read only memory does not need to bias a certain voltage on a control gate for programming and thereby injecting hot carriers onto the floating gate, and wherein the erasable programmable read only memory is capped by dielectric materials which are transparent to ultraviolet (UV) light.

REFERENCES:
patent: 4371956 (1983-02-01), Maeda et al.
patent: 4665503 (1987-05-01), Glasser
patent: 6128232 (2000-10-01), Keller et al.

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