Multilayer integrated circuit copper plateable barriers

Details Multilayer integrated circuit copper plateable barriers Multilayer integrated circuit copper plateable barriers

2005-05-31

2005-05-31

Nguyen, Thanh (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S680000, C438S681000, C438S686000, C438S687000, C438S650000

Reexamination Certificate

active

06900127

ABSTRACT:
A trench (70) is formed in a dielectric layer (20). A first metal layer (80) is formed in the trench using physical vapor deposition. A second metal layer (100) is formed in the trench (70) over the first metal layer (80) using chemical vapor deposition. Copper (110) is used to fill the trench (70) by electroplating copper directly onto the second metal (100).

REFERENCES:
patent: 6074945 (2000-06-01), Vaartstra et al.
patent: 6518668 (2003-02-01), Cohen
patent: 2002/0015855 (2002-02-01), Sajoto et al.
patent: 2002/0185671 (2002-12-01), Kim
patent: 2004/0028882 (2004-02-01), Andricacos et al.
Stanley Wolf, Silicon Processing for the VLSI ERA, 1986, vol. 1, pp. 335-353.

Affiliated with

Also associated with

Rating

Multilayer integrated circuit copper plateable barriers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multilayer integrated circuit copper plateable barriers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multilayer integrated circuit copper plateable barriers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3391106