Method and system to promote arbitration priority in a...

Details Method and system to promote arbitration priority in a... Method and system to promote arbitration priority in a...

2005-05-03

2005-05-03

Dang, Khanh (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S242000

Reexamination Certificate

active

06889283

ABSTRACT:
A technique is provided for prioritizing access to a bus for read completion transactions. The technique incorporates logic within an ASIC bridge, wherein split completion transactions are designated a priority level that facilitates the delivery of the requested data to a periphery device. Particularly, logic within the ASIC grants a read completion transaction a level one priority designation, which provides access to the bus to a requesting device prior to devices designated with a level two priority designation.

REFERENCES:
patent: 4785394 (1988-11-01), Fischer
patent: 5909594 (1999-06-01), Ross et al.
patent: 6175889 (2001-01-01), Olarig
patent: 6266731 (2001-07-01), Riley et al.
patent: 6480917 (2002-11-01), Moertl et al.

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