Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-07-05
2005-07-05
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S207000, C712S016000
Reexamination Certificate
active
06915388
ABSTRACT:
A multiprocessor computer system includes a plurality of processor nodes, a memory, and an interconnect network connecting the plurality of processor nodes to the memory. The memory includes a plurality of lines and a cache coherence directory structure. The plurality of lines includes a first line. The cache coherence directory structure includes a plurality of directory structure entries. Each directory structure entry includes processor pointer information indicating the processor nodes that have cached copies of the first line. The processor pointer information includes a plurality n of bit vectors, where n is an integer greater than one. The n bit vectors define a matrix having a number of locations equal to the product of the number of bits in each of the n bit vectors. The number of locations is greater than the number of processor nodes and each of the processor nodes is mapped to a corresponding one of the locations wherein the locations corresponding to the processor nodes are dispersed in the matrix in an at least partially noncontiguous manner.
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Bataille Pierre-Michel
Silicon Graphics Inc.
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