Semiconductor device and manufacturing method thereof

Details Semiconductor device and manufacturing method thereof Semiconductor device and manufacturing method thereof

2005-07-05

2005-07-05

Eckert, George (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000, C257S365000, C257S366000, C257S072000

Reexamination Certificate

active

06914302

ABSTRACT:
In a CMOS circuit formed on a substrate101, a subordinate gate wiring line (a first wiring line)102aand main gate wiring line (a second wiring line)107aare provided in an n-channel TFT. The LDD regions113overlaps the first wiring line102aand does not overlap the second wiring line107a. Thus, when a gate voltage is applied to the first wiring line, the GOLD structure is formed, while no applying forms the LLD structure. In this way, the GOLD structure and the LLD structure can be used appropriately in accordance with the respective specifications required for the circuits.

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